Product Summary

The EP1C3T144C8N is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, the EP1C3T144C8N is a cost-effective solution for data-path applications.

Parametrics

EP1C3T144C8N absolute maximum ratings: (1)On the condition of with respect to ground, VCCINT Supply voltage: min=-0.5V, max=2.4V; VCCIO: min=-0.5V, max=4.6V ; (2)VI DC input voltage: min=-0.5V, max=4.6V; (3)IOUT DC output current, per pin: min=-25mA, max=25mA; (4)On the condition of no bias, TSTG Storage temperature: min=-65℃, max=150℃; (5)On the condition of under bias, TAMB Ambient temperature: min=-65℃, max=135℃; (6)On the condition of BGA packages under bias, TJ Junction temperature: max=135℃.

Features

EP1C3T144C8N features: 1)Up to 294,912 RAM bits (36,864 bytes); (2)Supports configuration through low-cost serial configuration device; (3)Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards; (4)Support for 66-MHz, 32-bit PCI standard; (5)Low speed (311 Mbps) LVDS I/O support; (6)Up to two PLLs per device provide clock multiplication and phase shifting; (7)Up to eight global clock lines with six clock resources available per logic array block (LAB) row; (8)Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM.

Diagrams

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
EP1C3T144C8N
EP1C3T144C8N


IC CYCLONE FPGA 2910 LE 144-TQFP

Data Sheet

0-1: $7.38
Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
EP1C12
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